(1) Field of the Invention
This invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to form a crown shaped, capacitor structure, for a dynamic random access memory, (DRAM), device.
(2) Description of Prior Art
To increase performance of DRAM devices, the semiconductor industry has concentrated on increasing the signal, or capacitance, of the DRAM capacitor structure. The use of crown shaped, or cylindrical shaped, stacked capacitor structures, has allowed the desired capacitance increases to be realized via the additional surface area offered with the use of crown shaped storage node structures. However the topography of the crown shaped storage node structure, can lead to difficulties when attempting to fabricate a polysilicon capacitor upper plate structure, overlying the severe underlying topography. The definition of the polysilicon capacitor upper plate structure, via conventional photolithographic and dry etching procedures, is aggravated by the height of the vertical features, and by the spaces between the vertical features, of the underlying crown shaped storage node structure. The use of thick photoresist layers, needed to insure filling of the spaces between the vertical features of the crown shaped storage node structures, can result in a decreasing resolution of photoresist shape used to define the capacitor upper plate structure. In addition the anisotropic, reactive ion etching, (RIE), needed to define the capacitor upper plate structure, becomes more difficult when attempting to remove regions of polysilicon located on the vertical sides of the underlying crown shaped storage node structures.
This invention will describe a process for creating a crown shaped capacitor structure, featuring the use of a spin-on glass, (SOG), layer, used overlying the polysilicon layer that will be subjected to the definition procedures used for the polysilicon capacitor upper plate structure. The use of the planarizing SOG layer alleviates the severity of the subsequent photolithographic and dry etching procedures, used for definition of the capacitor upper plate structure. After definition of the polysilicon, capacitor upper plate structure, for the crown shaped capacitor structure, the SOG layer is selectively removed via use of a buffered hydrofluoric acid solution. Prior art such as Matsuura, in U.S. Pat. No. 5,937,322, as well as Lin et al, in U.S. Pat. No. 5,700,731, describe processes for fabricating crown shaped capacitor structures, however those prior arts do not describe the novel use of a disposable SOG layer, normalizing the severe topography of the underlying crown shaped storage node structure, reducing the severity of subsequent photolithographic and RIE procedures, used to define an overlying polysilicon capacitor upper plate structure.